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AIC1574
5-bit DAC, Synchronous PWM Power Regulator with Triple Linear Controllers
n FEATURES
l l
n DESCRIPTION
The AIC1574 combines a synchronous voltage mode controller with three linear controller as well as the monitoring and protection functions in this chip. The PWM controller regulates the microprocessor core voltage with a synchronous rectified buck converter. The three linear controllers regulate power for the 1.5V or 3.3V AGP bus power, the 1.5V GTL bus and the 1.8V power for the chip set core voltage and/or cache memory circuits. An integrated 5 bit D/A converter that adjusts the core PWM output voltage from 2.1V to 3.5V in 0.1V increments and from 1.3V to 2.05V in 0.05V increments. The linear controller for AGP bus power is selectable by TTL-compatible SELECT pin status for 1.5V or 3.3V with 3% accuracy. The other two linear controller provide 1.5V3% and 1.8V3% or adjustable output voltage by means of external d ivided resistor based on FIX pin status. This chip monitors all the output voltages. Power Good signal is issued when the core voltage is within 10% of the DAC setting and the other levels are above their under-voltage levels. Over-voltage protection for the core output uses the lower Nchannel MOSFET to prevent output voltage above 116% of the DAC setting. The PWM over-current function monitors the output current by using the voltage drop across the upper MOSFET's RDS(ON), eliminating the need for a current sensing resistor.
Compatible with HIP6021. Provides 4 Regulated Voltages for Microprocessor Core, AGP Bus, Memory and GTL Bus Power.
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TTL Compatible 5-bit Digital-to-Analog Core Output Voltage Selection. Range from 1.3V to 3.5V. 0.1V Steps from 2.1V to 3.5V. 0.05V Steps from 1.3V to 2.05V.
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1.0% Output Voltage for VCORE, 3.0% Accuracy for Linear Controller Outputs.
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Simple Voltage-Mode PWM Control and Built in Internal Compensation Networks.
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N-Channel MOSFET Driver for PWM Buck Converter.
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Linear Controller Drives Compatible with both N - Chanel MOSFET and NPN Bipolar Series Pass Transistor.
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Operates from +3.3V, +5V and +12V Inputs. Fast Transient Response. Full 0% to 100% Duty Ratios. Adjustable Current Limit without External Sense Resistor.
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Microprocessor Core Voltage Protection against Upper MOSFET shorted to +5V.
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Power Good Output Voltage Monitor. Over-Voltage and Over-Current Fault Monitors. 200KHz Free-Running Oscillator Programmable up to 700KHz.
n APPLICATIONS
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Full Motherboard Power Regulation for Computers.
Analog Integrations Corporation 4F, 9, Industry E. 9th Rd, Science Based Industrial Park, Hsinchu Taiwan, ROC DS-1574-00 May 22, 01 TEL: 886-3-5772500 FAX: 886-3-5772510
www.analog.com.tw
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AIC1574
n TYPICAL APPLICATION
+12VIN 10 2.2 F
VCC 28 +3.3VIN L1 VAUX 16 23 OCSET1 UGATE1 PHASE1 VOUT1 L1 + 1 H GND Q1 +5VIN
VOUT2 3.3V or 1.5V
Q3
DRIVE2 1 VSEN2 10
27 26
+ 25 COUT2 24 SELECT 11 22
LGATE1 Q2 PGND D5820
+ COUT1
VSEN1
Q4 VOUT3 1.5V +
DRIVE3
18 21
FB
VSEN3
19
COUT3 SD 9 20 7 15 6 5 14 4 + COUT4 FIX 2 8 13 17 GND 12 3 NC
VID0 VID1 VID2 VID3 VID4 PGOOD FAULT/RT SS
Q5
DRIVE4
VOUT4 1.8V
VESN4
Css
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AIC1574
n ORDERING INFORMATION
AIC1574-CX
PACKAGING TYPE S: SMALL OUTLINE
ORDER NUMBER
AIC157 4CS (SO2 8)
PIN CONFIGURATION
DRIVE2 FIX 1 2 28 VCC 27 UGATE1 26 PHASE1 25 LGATE1 24 PGND 23 OCSET 22 VSEN1 21 FB 20 NC 19 VSEN3 18 DRIVE3 17 GND 16 VAUX 15 DRIVE4
VID 4 3 VID 3 4 VID 2 5 VID 1 6 VID0 7 PGOOD 8 SD 9 VSEN2 10 SELECT 11 S S 12 FAULT/RT 13 VSEN4 14
n ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC .................. ... ... ... ... ........ ... ... ... ...... ... ...... ..... ... ..................... +15V PGOOD, FAULT and GATE Voltage ...... ... ... ... ........ ... ... ..... .... GND -0.3V to VCC +0.3V Input, Output , or I/O Voltage ......... ...... ... ... ... ... ... ... ... ..... ... ............ GND -0.3V to 7V
Recommended Operating Conditions Supply Voltage; VCC... ... .................. ... ... ... ..................... +12V10% Ambient temperature Range ... ... ..... ... ... ... ... ... ................. 0C~70C Junction Temperature Range ... ... ......... ..... ... .................. 0C~125C Thermal Information Thermal Resistance, JA SOIC package ... ... ... ... ... ... ... ... ... ... ... ..... ... ..... ... .............. 70C/W SOIC package (with 3in2 of copper) ... ...... ... ... ............ ......... 50C/W Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range ... ... ... ... ... ... ... ..... ... ...... 150C
... ... ... ... ... ... ... ... ... ... ... .... -65C ~ 150C ... ... ... ... ... ... ... ... ... ... ..... ... 300C
Maximum Lead Temperature (Soldering 10 sec)
n TEST CIRCUIT
Refer to APPLICATION CIRCUIT.
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AIC1574
n ELECTRICAL CHARACTERISTICS
PARAMETER VCC SUPPLY CURRENT Supply Current POWER ON RESET Rising VCC Threshold Falling VCC Threshold Rising VAUX Threshold VAUX Threshold Hysteresis Rising VOCSET1 Threshold OSCILLATOR Free Running Frequency Total Variation Ramp. Amplitude REFERENCE AND DAC DAC (VID0~VID4) Input Low Voltage DAC (VID0~VID4) Input High Voltage DACOUT Voltage Accuracy Bandgap Reference Voltage Bandgap Reference Tolerance LINEAR REGULATOR (OUT2, OUT3, OUT4) Regulation VSEN2 Regulation Voltage VSEN2 Regulation Voltage VSEN3 Regulation Voltage VSEN3 Regulation Voltage Under-Voltage Level ( VSEN/VREG) Under-Voltage Hysteresis (V SEN/VREG) Output Drive Current (All Linears ) VSEN Rising VSEN Falling VAUX -V DRIVE > 0.6V Select<0.8V Select>2.0V VDAC=1.8V~3.5V RT=Open 6k(Vcc=12V, TJ=25C, Unless otherwise specified) SYMBOL MIN. TYP. MAX. UNIT
UGATE, LGATE, GATE3 and VOUT2 open
ICC
3
mA
VCCTHR VCCTHF VAUXTHR VAUXHYS VOCSETH F VOSC 170 -15 1.5 8.2 2.5 500 1.26 200
10.4
V V V mV V
230 +15
KHz % VP-P
VIDL VIDH 2.0 -1.0 VREF -2.5 1.265
0.8
V V
+1.0
% V
+2.5
%
3 VREG2 VREG2 VREG3 VREG4 VSENUV 1.5 3.3 1.5 1.8 75 5 20 30
% V V V V % % mA
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AIC1574
n ELECTRICAL CHARACTERISTICS
PARAMETER TEST CONDITIONS SYNCHRONOUS PWM CONTROLLER AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate (G.B.D.) (G.B.D.) (G.B.D.) note 1.
(Continued)
SYMBOL
MIN.
TYP.
MAX.
UNIT
80 GBWP SR 13 6
dB MHz V/s
PWM CONTROLLER GATE DRIVER Upper Drive Source Upper Drive Sink Lower Drive Source Lower Drive Sink PROTECTION VSEN1 Over-Voltage ( VSEN1 /DACOUT ) FAULT Sourcing Current OCSET Current Source Soft-Start Current POWER GOOD VSEN1 Upper Threshold ( VSEN1 /DA COUT ) VSEN1 Under-Voltage ( VSEN1/DACOUT ) VSEN1 Hysteresis (VSEN1/DACOUT) PGOOD Voltage Low VSEN1 Rising VSEN Falling Upper and Lower Threshold IPGOOD=-4mA VPGOOD 108 92 2 0.4 0.8 111 95 % % % V VSEN1 Rising VCC-VFAULT/RT =2.0V VOCSET =4.5VDC OVP IOVP IOCSET ISS 170 116 20 200 25 230 120 % mA A A VCC=12V, VUGATE = 6V VUGATE=1V VCC=12V, VLGATE =6V VLGATE=1V IUGH RUGL ILGH RLGL 0.9 2.8 1 2.2 3.0 3.5 A A
Note 1. Without internal compensation network, the gain bandwidth product is 13MHz. Being associated with internal compensation networks, the Bode Plot is shown in Fig. 3, "Internal Compensation Gain of PWM Error Amplifier".
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AIC1574
n TYPICAL PERFORMANCE CHARACTERISTICS
PGOOD SS
SS VOUT3 VOUT4
VDAC=3.5V
VDAC=2V
VOUT2 VOUT1
VDAC=1.3V
Fig. 1 Soft Start Interval with 4 Outputs and P GOOD
Internal Compensation Gain of PWM Error Amplifier
30
Fig. 2
Soft Start Initiates PWM Output R T Resistance vs. Frequency
10M
90 C
25
RT Pull Up to 12V
1M
Gain (dB)
-40 C 22C
15
Resistance ()
20
100k
RT Pull Down to GND
10
5
10k
0
-5 1k 10k 100k 1M
1k 10k
100k
1M
Fig. 3
Frequency (Hz)
Supply Current vs. Frequency
Fig. 4
Switching Frequency (Hz)
Over Current ON Inductor
120
VCC=12V
100
Over Load
CUG1=C LG1=C
C=4.7nF
Applied
Inductor Current 5A/div
80
ICC (mA)
C=3.3nF
60
C=1.5nF
40
SS
C=680pF
20
Fault
0 200k
C=0
300k 400k 500k 600k 700k 800k 900k 1M
Fig. 5
Switching Frequency (Hz)
Fig. 6
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AIC1574
n TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Temperature vs. Switching Frequency Drift
4 3
FSW=200KHz
Switching Frequency Drift (%)
0.1A to 3A Load Step
2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -40 -20 0 20 40 60 80 100 120
VOUT
Fig. 7 Load Transient of Linear Controller
Temperature vs. OCSET Current Drift
6 5
0.4
Fig. 8
Temperature (C) Temperature Drift of 9 Different Parts
OCSET Current = 200 A
0.3
OCSET Current Drift (%)
4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -40 -20 0 20 40 60 80 100 120
VSEN2 Voltage Drift (%)
0.2 0.1 0.0
-0.1
-0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -40
VREG2=3.3V
-20 0 20 40 60 80 100 120
Fig. 9
0.4
0.3
Temperature (C)
Temperature Drift of 13 Different Parts
0.4 0.3
Fig. 10
Temperature ( C)
Temperature Drift of 9 Different Parts
PWM Output Voltage Drift (%)
0.1 0.0 -0. 1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -40 -20 0
20 40 60 80 100 120
VSEN4 Voltage Drift (%)
0.2
0.2 0.1 0.0
-0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -40
DACOUT=1.6V
VREG4=1.8V
-20 0 20 40 60 80 100 120
Fig. 11
Temperature ( C)
Fig. 12
Temperature (C)
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AIC1574
n TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
0 to 20A Load Step
V OUT1
0 to 20A Load Step
VOUT1
Fig. 13
Load Transient of PWM Output
Fig. 14
Stringent Load Transient of PWM Output
FB Voltage Accuracy
70 60
Bandgap Voltage Accuracy
Mean=1.266V
60
DACOUT=1.6V Mean= -0.03% Ta = 25 C
FIX=0V Ta = 25 C
50
3 std.= 0.8%
Number of Parts
-0.2 0.0 0.2 0.4 0.6
3 std.= 0.56%
Number of Parts
50
40
40
30
30
20
20
10
10
0 -0.6 -0.4
0 1.255 1.260 1.265 1.270 1.275
Fig. 15
Accuracy (%)
Fig. 16
Bandgap Voltage (V)
8
VSEN3
FIX
VSEN1
PGOOD
INHB
VAUX LUV UP CURRENT LATCH 4V x 110% SS OV 0.2V R COUNTER (3) R LATCH x 116% FAULT / RESET POR RAMP1 200uA SOFT START LOGIC VID0 VID1 DACOUT TTL D/A CONVERTER VID3 SS OFF VCC VID4 VID2 OSCILLATOR RT FAULT VCC OC1 R X 75% OVER X 90%
n BLOCK DIAGRAM
DRIVE3
VAUX
1.26V
DRIVE4
INHB
VSEN4
SD
OCSET1
VAUX
VCC
POWER
POR
ON
RESET
VSEN1
INHB VCC DRV-H
25uA SS INHB
VAUX
x 75%
DRIVE2 VCC
GATE CONTROL COMP1 DRV-L RAMP1 Comp. 3 P, 2Z ERROR AMP1
4.5V
SS
1.5V or 3.3V
GND
VSEN2 PHASE1 UGATE1
SELECT
LGATE1
PGND
NC
FB
AIC1574
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AIC1574
n PIN DESCRIPTION
Pin 1: DRIVE2: Connect this pin to the Gate of the external N-MOS to supply AGP power. Pin 2 : FIX: Left this pin open, its Pin 9 : the other outputs are below their under-voltage thresholds. The PGOOD output is open for VID codes that inhibit operation. See Table 1. SD: A TTL-compatibe voltage is pulled high, enabling fixed output voltage operation for 1.5V and 1.8V linear regulators. If connect this pin to Ground, the new output voltage set by external resistors RGND (Connected between VSEN and GND) and ROUT (Connected between VSEN and VOUT) . logic level high signal applied this pin immediately discharges the soft-start capacitors, disabling all the outputs. Dedicated internal circuitry insures the core output voltage does not go nective during this process. When re-enabled, this IC undergoes a new soft-start cycle. Left open, this pin is pulled low by an internal pull-down resistor, enabling operation. Pin 10:VSEN2: Connect this pin to the output of 5bit DAC voltage select pin. TTLcompatible inputs used to set the internal voltage reference VDAC. When left open, these pins are internally pulled up to 5V and provide logic ones. The level of VDAC sets the converter output voltage as well as the PGOOD and OVP thresholds. Table 1 specifies the VDAC voltage for the 32 combinations of DAC inputs. Pin 8: PGOOD: Power good indicator pin. the AGP linear regulator. The voltage at this pin is regulated to the 1.5V/3.3V predetermined by the logic Low/High level ststus of the SELECT pin. This pin is also monitored events. Pin 11:SELECT: This pin determines the output voltage of the AGP bus linear regulator. A low TTL input sets the output voltage to 1.5V, while a high input sets the output voltage to 3.3V. for under-voltage
VOUT
Pin 7: VID4: Pin 6: VID3: Pin 5: VID2: Pin 4: VID1: Pin 3: VID0:
1.265V x (R GND + ROUT ) = RGND
PGOOD is an open drain output. This pin is pulled low when the converter output is 10% out of the VDAC reference voltage and
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AIC1574
Pin 12:SS: Soft-start pin. Connect a capacitor from this pin to ground. This capacitor, along with an internal 25A (typically) current source, sets the soft-start interval of the converter. Pulling this pin low will shut down the IC. Pin 13: FAULT/RT: Frequency adjustment pin. Connecting a resistor (RT) Pin 20: NC: Pin 21: FB: from this pin to GND, increasing the frequency. Connecting a resistor (RT) from this pin to VCC, decreasing the frequency by the following figure (Fig. 4). This pin is 1.26V during normal operation, but it is pulled to VCC in the event of an overvoltage or over-current condition. Not Connected. The error amplifier inverting input pin. Pin 22: VSEN1: Converter output voltage sense pin. Connect this pin to the converter output. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for over-voltage protection function. Pin 23: OCSET:Current limit sense pin. Connect a resistor R OCSET from this pin to the drain of the external highside N-MOSFET. ROCSET , an internal 200A (IOCSET ), and current the source Nupper Pin 19: VSEN3: Connect this pin to the 1.5V linear regulator's output. This pin is monitored for undervoltage events. Pin 17: GND: Signal GND for IC. All voltage levels are measured with respect to this pin. Pin 18: DRIVE3: Connect this pin to the Gate of the external N-MOS for providing 1.5V power to GTL bus.
25 .2K , RT pulled to f = f0 1 + RT GND VCC - 1.26V f = f0 1 - 5 x RT pulled to VCC, ,
RT
where f0 is free run frequency. Pin14: VSEN4: Connect this pin to
MOSFET on-resistance (RDS(ON)) set the over-current trip point according to the following equation: the 1.8V linear regulator's output. This pin is monitored for undervoltage events. Pin15: DRIVE4: Connect this pin to Pin 24:PGND:
IPEAK =
IOCSET x R OCSET R DS(ON)
the Gate of the external N-MOS to drive for the 1~8V power. Pin 16: VAUX: This pin provides boost current for the linear regulator's output. The voltage at this pin is also monitored for power-on-reset purpose. Driver power GND pin. PGND should be connected to a low impedance close source. to ground lower plane in N-MOSFET
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AIC1574
Pin 25: LGATE: Lower N-MOSFET gate drive pin. Pin 26: PHASE: Over-current detection pin. Connect the PHASE pin to source of the external upper N-MOSFET. This pin detects the voltage drop across the upper N-MOSFET RDS(ON) for over-current protection. Pin 27: UGATE: Connect UGATE to pin of the exPin 28: VCC: ternal upper N-MOSFET gate. The chip power supply pin. It also provides the gate bias charge for all the MOSFETs controlled by the IC. Recommended supply voltage is 12V. The voltage at this pin is monitored for Power-OnReset purpose.
n APPLICATION INFORMATIONS
The AIC1574 is designed for microprocessor computer applications with 3.3V and 5V power, and 12V bias input. This IC has one synchronous PWM controller and three linear controllers. The PWM controller is designed to regulate the microprocessor core voltage (V OUT1 ) by driving 2 MOSFETs (Q1 and Q2) in a synchronous rectified buck converter configuration. The core voltage is regulated to a level programmed by the 5-bit D/A converter. One of the linear controllers is designed to regulate the advanced graphic port (AGP) bus voltage (V OUT2) to a digitally programmable level 1.5V or 3.3V. Selection of either output voltage is achieved by applying the proper logic level at the SELECT pin. The remaining two linear controllers supply the 1.5V GTL bus power (V OUT3) and 1.8V memory power (V OUT4). All linear controllers are designed to employ an external pass transistor. The Power-On Reset (POR) function continually monitors the input supply voltage +12V at VCC pin, the 5V input voltage at OCSET pin, and the 3.3V input at VAUX pin. The POR function initiates soft-start operation after all three input supply voltage exceed their POR thresholds. PWM error amplifier reference input (Non-inverting terminal) and output is clamped to a level proportional to the SS pin voltage. As the SS pin voltage slew from 1V to 4V, the output clamp generates PHASE pulses of increasing width that charge the output capacitors. After the the output voltage increases to approximately 70% of the set value, the reference input clamp slows the output voltage rate-to rise and provides a smooth transition to the final set voltage. Additionally, all linear regulator's reference inputs are clamped to a voltage proportional to the SS pin voltage. This method provides a rapid and controlled output voltage rise. Fig. 1 and Fig. 2 show the soft-start sequence for the typical application. The internal oscillator's triangular waveform is compared to the clamped error amplifier output voltage. As the SS pin voltage increases, the pulse width on PHASE pin increases. The interval of increasing pulse width continues until output reaches sufficient voltage to transfer control to the input reference clamp. Each linear output initially follows a ramp. When each output reaches sufficient voltage the input reference clamp slows the rate of output voltage rise. The PGOOD signal toggles `high' when all output voltage levels have exceeded their under-voltage levels. The POR function initiates the soft-start sequence. An internal 2 5A current source charges an external capacitor (CSS) on the SS pin from 0V to 4.5V. The
Soft-Start
Fault Protection
All four outputs are monitored and protected against
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AIC1574
extreme overload. A sustained overload on any output or over-voltage on PWM output disable all converters and drive the FAULT/RT pin to VCC.
OVER CURRENT LATCH LUV OC1 S R Q
INHIBIT
0.15V SS
+
S COUNTER R
FAULT LATCH S VCC Q FAULT
+ 4.0V OV
POR
R
Fig. 17 Simplified Schematic of Fault Logic A simplified schematic is shown in figure 1 An 7. over-voltage detected on VSEN1 immediately sets the fault latch. A sequence of three over-current fault signals also sets the fault latch. An undervoltage event on either linear output (VSEN2, VSEN3, VSEN4) is ignored until the soft-start interval. Cycling the bias input voltage (+12V off then on) resets the counter and the fault latch. A separate over-voltage circuit provides protection during the initial application of power. For voltage on VCC pin below the power-on reset (and above ~4V), should VSEN1 exceed 1.0V, the lower MOSFET (Q2) is driven on as needed to regulate VOUT1 to 1.0V.
Over-Current Protection Gate Drive Overlap Protection
The Overlap Protection circuit ensures that the Bottom MOSFET does not turn on until the Upper MOSFET source has reached a voltage low enough to ensure that shoot-through will not occur. All outputs are protected against excessive overcurrent. The PWM controller uses upper MOSFET's on-resistance, RDS(ON) to monitor the current for protection against shorted outputs. All linear controllers monitor VSEN for under-voltage events to protect against excessive current.
Over-Voltage Protection
During operation, a short on the upper PWM MOSFET (Q1) causes V OUT1 to increase. When the output exceed the over-voltage threshold of 116% of DACOUT, the FAULT pin is set to fault latch and turns Q2 on as required in order to regulate VOUT1 to 115% of DACOUT. The fault latch raises the FAULT/RT pin close to VCC potential.
When the voltage across Q1 (IDERDS(ON)) exceeds the level (200A EROCSET ), this signal inhibit all outputs. Discharge soft-start capacitor (Css) with 25A current sink, and increments the counter. Css recharges and initiates a soft-start cycle again until the counter increments to 3. This sets the fault latch to disable all outputs. Fig. 6 illustrates the over-current protection until an over load on OUT1. Should excessive current cause VSEN to fall below
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AIC1574
the linear under-voltage threshold, the LUV signal sets the over-current latch if C is fully charged. SS Cycling the bias input power (off then on ) reset the counter and the fault latch. The over-current function for PWM controller will trip at a peak inductor current (IPEAK) determined by: OUT3 and OUT4 Voltage Program The GTL bus voltage (1.5V, OUT3) and the chip set and/or cache memorey voltage (1.8V,OUT4) are internally set for simpe, low cost implementation base on the FIX pin left open. Grounding FIX pin a llows both output voltages to be set by means of external resistor dividers.
3.3V
The status of the SELECT pin can not be changed during operation of the IC without immediatelly causing a fault condition.
IPEAK =
IOCSET x R OCSET R DS(ON)
The OC trip point varies with MOSFET's temperature. To avoid over-current tripping in the normal operating load range, determine the R OCSET resistor from the equation above with: 1. The maximum RDS(ON) at the temperature. 2. The minimum IOCSET from the specification table. 3. Determine PEAK > IOUT(MAX) + (inductor ripple I current) /2.
DRV VOUT + ROUT VSEN FIX RGND AIC1574
PWM OUT1 Voltage Program The output voltage of the PWM converter is programmed to discrete levels between 1.3V to 3.5V. The VID pins program an internal voltage reference (DACOUT) through a TTL compatible 5 bit digital to analog converter. The VID pins can be left open for a logic 1 input, because they are internally pulled up to 5V by a 70K resistor. Changing the VID inputs during operation is not recommended. All VID pin combinations resulting in an INHIBIT disable the IC and the open collector at the PGOOD pin.
R VOUT = 1 .265V x 1 + OUT R GND

Adjusting the Output Voltage of OUTPUT 3 and 4
Shutdown
The AIC1574 features a dedicated shetdown pin (SD). A TTL-compatible logic high signal applied to this pin shuts down all four outputs and discharge the soft-start capacitor. The VID codes resulting in an INHIBIT as shown in Table 1 also shut down the IC.
OUT2 Voltage Program
The AGP regulator output voltage is internally set to one of two discrete levels based on the SELECT pin status. Left SELECT pin open, internal pulled high, the output voltage is 3.3V. Grounding SELECT pin to GROUND will get the 1.5V output voltage.
n APPLICATION GUIDE LINES
Layout Considerations
Any inductance in the switched current path generates a large voltage spike during the switching interval. The voltage spikes can degrade efficiency,
14
AIC1574
radiate noise into the circuit, and lead to device over-voltage stress. Careful component selection and tight layout of critical components, and short, wide metal trace minimize the voltage spike. A ground plane should be used. Locate the input capacitors (CIN) close to the power switches. Minimize the loop formed by CIN, the upper MOSFET (Q1) and the lower MOSFET (Q2) as possible. Connections should be as wide as short as possible to minimize loop inductance. The connection between Q1, Q2 and output inductor should be as wide as short as practical. Since this connection has fast voltage transitions will e asily induce EMI. The output capacitor (COUT ) should be located as close the load as possible. Because minimize the transient load magnitude for high slew rate requires low inductance and resistance in circuit board The AIC1574 is best placed over a quiet ground plane area. The GND pin should be connected to the groundside of the output capacitors. Under no circumstances should GND be returned to a ground inside the C , Q1, Q2 loop. The GND and PGND IN pins should be shorted right at the IC. This help to minimize internal ground disturbances in the IC and prevents differences in ground potential from disrupting internal circuit operation. The wiring traces from the control IC to the MOSFET gate and source should be sized to carry peak current. The Vcc pin should be decoupled directly to GND by a 2.2F ceramic capacitor, trace lengths should be as short as possible.
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AIC1574
Table 1 VOUT1 Voltage Program (0=connected to GND, 1=open or connected to 5V) For all package versions PIN NAME VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 DACOUT VOLTAGE 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80 V 1.85 V 1.90 V 1.95 V 2.00 V 2.05 V VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 PIN NAME VID3 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 DACOUT VOLTAGE INHIBIT 2.1 V 2.2 V 2.3 V 2.4 V 2.5 V 2.6 V 2.7 V 2.8 V 2.9 V 3.0 V 3.1 V 3.2 V 3.3 V 3.4 V 3.5 V
A multi-layer-printed circuit board is recommended. Figure 11 shows the connections of the critical components in the converter. The CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer.
tude, the output voltage transient change due to the output capacitor can be note by the following equation:
VOUT = ESR x IOUT + ESL x
IOUT is transient load current step.
IOUT T ,
where
After the initial transient, the ESL dependent
PWM Output Capacitors
The load transient for the microprocessor core requires high quality capacitors to supply the high slew rate (di/dt) current demand. The ESR (equivalent series resistance) and ESL (equivalent series inductance) parameters rather than actual capacitance determine the buck capacitor values. For a given transient load magni-
term drops off. Because the strong relationship between output capacitor ESR and output load transient, the output capacitor is usually chosen for ESR, not for capacitance value. A capacitor with suitable ESR will usually have a larger capacitance value than is needed for energy storage. A common way to lower ESR and raise ripple
16
AIC1574
current capability is to parallel several capacitors. In most case, multiple electrolytic capacitors of small case size are better than a single large case capacitor. current without saturation, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss
Input Capacitor Selection Output Inductor Selection
Inductor value and type should be chosen based on output slew rate requirement, output ripple requirement and expected peak current. Inductor value is primarily controlled by the required current response time. The AIC1570 will provide either 0% or 100% duty cycle in response to a load transient. The response time to a transient is different for the application of load and remove of load. Most of the input supply current is supplied by the input bypass capacitor, the resulting RMS current flow in the input capacitor will heat it up. Use a mix of input bulk capacitors to control the voltage overshoot across the upper MOSFET. The ceramic capacitance for the high frequency decoupling should be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedance. The buck capacitors to supply the RMS current is approximate equal to:
tRISE =
L x IOUT L x IOUT tFALL = VIN - VOUT , VOUT .
Where IOUT is transient load current step.
IRMS = (1- D) x D x I2 OUT +
1 VIN x D x 12 f x L
2
D=
In a typical 5V input, 2V output application, a 3H inductor has a 1A/S rise time, resulting in a 5S delay in responding to a 5A load current step. To optimize performance, different combinations of input and output voltage and expected loads may require different inductor value. A smaller value of inductor will improve the transient response at the expense of increase output ripple voltage and inductor core saturation rating. Peak current in the inductor will be equal to the maximum output load current plus half of inductor ripple current. The ripple current is approximately equal to: , where
VOUT VIN
The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage.
PWM MOSFET Selection
In high current PWM application, the MOSFET power dissipation, package type and heatsink are the dominant design factors. The conduction loss is the only component of power dissipation for the lower MOSFET, since it turns on into near zero voltage. The upper MOSFET has conduction loss and switching loss. The gate charge losses are proportional to the switching frequency and are dissipated by the AIC1574. However, the gate charge increases the switching interval, tSW, which increase the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction tem-
(V IN - VOUT) x VOUT I RIPPLE = f x L x VIN ;
f = AIC1574 oscillator frequency. The inductor must be able to withstand peak
17
AIC1574
perature at high ambient temperature by calculating the temperature rise according to package thermal resistance specifications. breakdown voltage must be greater than twice the maximum input voltage.
PUPPER = IOUT 2 x RDS(ON) x D +
IOUT x VIN x tSW x f 2
Linear Controller MOSFET Selection
The power dissipated in a linear regulator is :
PLOWER = IOUT 2 x RDS(ON) x (1 - D)
The equations above do not model power loss due to the reverse recovery of the lower MOSFET's body diode. The RDS(ON) is different for the two previous equations even if the type devices is used for both. This is because the gate drive applied to the upper MOSFET is different than the lower MOSFET. Logic level MOSFETs should be selected based on on-resistance considerations, RDS(ON) should be chosen base on input and output voltage, allowable power dissipation and maximum required output current. Power dissipation should be calculated based primarily on required efficiency or allowable thermal dissipation. Rectifier Schottky diode is a clamp that prevent the loss parasitic MOSFET body diode from conducting during the dead time between the turn off of the lower MOSFET and the turn on of the upper MOSFET. The diode's rated reverse
PLINEAR = IOUT2 x (VIN2 - VOUT2 )
Select a package and heatsink that maintains junction temperature below the maximum rating while operation at the highest expected ambient temperature.
Linear Output Capacitor
The output capacitors for the linear regulator and linear controller provide dynamic load current. The linear controller uses dominant pole compensation integrated in the error amplifier and is insensitive to output capacitor selection. COUT2, COUT3 and COUT4 should be selected for transient load regulation.
PWM Feedback Analysis
VIN V OSC
Q1
VDAC
VEA PWM COMP. ERROR AMP. Compensation Networks Q2
LO CO RESR
VOUT +
Modulation Gain
18
AIC1574
The compensation network consists of the error amplifier and built in compensation networks. The goal of the compensation network is to provide for fast response and adequate phase margin. Phase Margin is the difference between the closed loop phase at 0dB and 180 degree. Gain are given by
FZ 1 = 2.6KHz ; FZ 2 = 24 KHz ; FP1 = 30 KHz ; FP 2 = 400 KHz
60
Closed Loop Gain(dB) = Modulation Gain(dB) + Compensation Gain (dB)
FZ1
40
F Z2
FP1
Compensation Gain
Modulation Gain(dB)
VIN 20 log V OSC
F + 10 log1 + F ESR
F + F xQ LC
2 2

2
Gain (dB)
20

F P2 20log(VIN/VOSC) FOdB
0
F - 10 log 1 - FLC where 1 FLC = 2 LO CO
2

-20 100
Modulation Gain FLC F
1k
F ESR
10k 100k
Closed Loop Gain
1M 10M
Frequency (KHz)
Bode Plot of Converter Gain Sampling theory shows that F0dB must be less that half the switching frequency for the loop stables. But it must be considerably less than that, or there will be large amplitude switching
; ;
FESR =
1 = Q
1 2 x RESR x CO
x R ESR +
CO LO
LO CO
x
1 R LOAD
frequency ripple at the output. Thus, the usual practices is to fix F0dB at 1/4 to 1/5 the switching frequency.
The break frequency of Internal Compensation
19
AIC1574
n
PHYSICAL DIMENSIONS
l 28 LEAD PLASTIC SO (unit: mm)
SYMBOL
D
MIN 2.35 0.10 0.33 0.23 17.70 7.40 10.00 0.40
MAX 2.65 0.30 0.51 0.32 18.10 7.60 10.65 1.27
A A1 B
E H
C D E e H L
e
A
1.27 (TYP)
A1
B
C
L
20

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